In recent years, as the processing size of semiconductor integrated circuit devices (which will be referred to as “semiconductor devices”) has been reduced, a combination of a copper interconnect and an insulating film having a small dielectric constant, i.e., a so-called low-k film has been used for multilayer interconnects of semiconductor devices. Use of such combination for multilayer interconnects allows reduction in RC delay and in power consumption. Furthermore, to achieve increase in the integration, function and operation speed of semiconductor devices, use of a low-k film having a lower dielectric constant has been under examination.
Copper interconnects are normally formed by damascene process. There are two types of damascene process, i.e., single damascene process in which an interconnect and a via plug are alternately formed and dual damascene process in which an interconnect and via plug are simultaneously formed.
Hereafter, a method for forming a multilayer interconnect employing damascene process will be described with reference to FIGS. 5(a) and 5(b).
As shown in FIG. 5(a), a first insulating film 102 is formed on a silicon substrate 101 and then a first copper interconnect 104 including a first barrier metal 103 is formed in the first insulating film 102. Note that transistors and the like, which are not shown in FIGS. 5(a) and 5(b), are formed over the silicon substrate 101. Then, a diffusion barrier film 105 for preventing diffusion of copper and a second insulating film 106 are formed in this order over the first insulating film 102 and the first copper interconnect 104. Subsequently, a via hole 106a is formed in the diffusion barrier film 105 and the second insulating film 106 and an interconnect trench 106b is formed in the second insulating film 106, thereby forming a recess portion 106c including the via hole 106a and the r interconnect trench 106b. Thereafter, a second barrier metal film 107 is formed so as to extend over wall surfaces of the recess portion 106c. In FIG. 5(a), as an upper barrier metal structure, the case where the second barrier metal film 107 has a single layer structure is shown. However, as shown in FIG. 5(b), a two-layer structure of a second barrier metal film 108 and a third barrier metal film 109 may be formed so as to extend over the wall surfaces of the recess portion 106c. 
Next, although not shown in the drawings, in the case of FIG. 5(a), a copper seed layer is formed on the second barrier metal film 107 (the third barrier metal film 109 in the case of FIG. 5(b)) and then the recess portion 106c is filled by copper plating using the seed layer as a seed and a copper film is formed so as to cover an entire surface of the second insulating film 106. Subsequently, CMP (chemical mechanical polishing) is performed to remove part of the copper film which is other than part of the copper film located inside of the recess portion 106c and is located over the second insulating film 106 and, in the case of FIG. 5(a) and part of the second barrier metal film 107 which is other than part of the second barrier metal film 107 located inside of the recess portion 106c and is formed on the second insulating film 106 (in the case of FIG. 5(b), parts of the third barrier metal film 109 and the second barrier metal film 108 which are other than parts thereof located inside of the recess portion 106c and are located on the second insulating film 106). Thus, one or both of an interconnect and a via plug can be formed. By repeating a series of this operation, a multilayer interconnect can be formed (see, for example, Patent Reference 1).
In general, copper is easily defused in an insulating film such as a silicon oxide film by heat or electric field and this causes degradation of characteristics of transistors in many cases. Moreover, copper has a poor adhesiveness with an insulating film. Accordingly, a method in which in forming a copper interconnect, a barrier metal film including a tantalum film or a tantalum nitride film is formed between copper and an insulating film to prevent diffusion of copper into the insulating film and improve an adhesiveness between the insulating film and the copper has been proposed (see, for example, Patent Reference 2). For example, the case where a barrier metal film has a single-layer structure of a tantalum film or a tantalum nitride film corresponds to the structure of FIG. 5(a) and the case where a barrier metal film has a two-layer structure including a tantalum film and a tantalum nitride film corresponds to the structure of FIG. 5(b).
However, for example, in the above-described example, when a high melting point metal film such as tantalum is used as the second barrier metal film 107 shown in FIG. 5(a), an adhesiveness between the second insulating film 106 including the recess portion 106c and the high melting point film is poor. To cope with the problem of the poor adhesiveness, for example, when a tantalum film is used as the third barrier metal film 109, as shown in FIG. 5(b), a tantalum nitride film is formed as the second barrier metal film 108 between the third barrier metal film 109 of a tantalum film and the second insulating film 106 to improve this poor adhesiveness. However, a sufficient adhesiveness can not be achieved by this method.
When a tantalum nitride film is used as the second barrier metal film 107 (in the case of FIG. 5(a)) or the third barrier metal film 109 (in the case of FIG. 5(b)), the tantalum nitride film is not oxidized but the tantalum nitride film has a high resistance and the problem of the poor adhesiveness is still left.
Furthermore, when a titanium film or a titanium nitride film is used as the second barrier metal film 107 (in the case of FIG. 5(a)) or the third barrier metal film 109 (in the case of FIG. 5(b)), the same problem as that in the above-described case where a tantalum film is used arises.
In forming the copper seed layer, PVD (physical vapor deposition) is normally used. With reduction in the size of semiconductor devices, an aspect ratio (i.e., the ratio between the depth and diameter of a via hole) of a via hole tends to be increased. Therefore, when a copper seed layer is formed using PVD, it is difficult to ensure a sufficient thickness of part of the copper seed layer located at the bottom of the via hole. When the part of the copper seed layer at the bottom of the via hold has a small thickness, a current for electrolytic plating can not be sufficiently supplied, so that the via hole can not be sufficiently filled by copper through electrolytic plating. For example, in the case of FIG. 5(a), the recess portion 106c including the via hold 106a and the interconnect trench 106b can not be filled by copper. Accordingly, product yield and reliability are reduced. In view of this point, to ensure a sufficient thickness of part of the copper seed layer at the bottom of the via hole, formation of the copper layer using CVD (chemical vapor deposition) has been examined. However, there are many cases where a substance, such as fluorine (F) and the like, which causes corrosion of copper is contained in a source gas, and thus this method has not been put in practical use yet.
Trial of forming a copper interconnect directly on a barrier metal film by electrolytic plating without using a copper seed layer has been under consideration.
However, for example, when a high-melting point metal film such as a tantalum film is used as the second barrier metal film 107 (in the case of FIG. 5(a)) or the third barrier metal film 109 (in the case of FIG. 5(b)) in the above-described example, in forming copper by electrolytic plating, tantalum is oxidized, so that a tantalum oxide film having a high resistance is formed. Therefore, increase in interconnect resistance can not be avoided.
To realize reduction in resistance of a barrier metal film, use of a metal which does not lose its conductivity even when being oxidized and a metal such as ruthenium, iridium and the like of which oxide itself has a low resistance draw attentions (see, for example, Patent References 3 an 4). Such a metal has a lower resistance than that of tantalum or tantalum nitride and does not lose its conductivity even when being oxidized. Therefore, without using a copper seed layer, copper plating can be directly performed onto the barrier metal film. Note that in general, such a metal is formed by atomic layer epitaxy or chemical vapor deposition.                Patent Reference 1: Japanese Laid-Open Publication No. 11-223755        Patent Reference 2: Japanese Laid-Open Publication No. 2002-43419        Patent Reference 3: Japanese Patent No. 3409831        Patent Reference 4: Japanese Laid-Open Publication No. 2002-75994        